核电子学与探测技术
覈電子學與探測技術
핵전자학여탐측기술
NUCLEAR ELECTRONICS & DETECTION TECHNOLOGY
2010年
2期
211-216,228
,共7页
锥束CT%FDK算法%存储机制%SDRAM控制器%SRAM%重建加速
錐束CT%FDK算法%存儲機製%SDRAM控製器%SRAM%重建加速
추속CT%FDK산법%존저궤제%SDRAM공제기%SRAM%중건가속
Cone CT%SDRAM%SRAM%memory controller%reconstruction acceleration
为了实现三维锥束CT图像重建加速系统的小型化,建立了基于FPGA的三维图像重建系统.并对该系统中所采用的FDK重建算法所需的数据存储量和数据传输量以及由SDRAM、SRAM和FPGA内部缓存组成的存储系统的数据吞吐率进行了研究.首先,根据FDK算法的滤波与反投影两个步骤介绍了三维锥束CT图像重建系统的数据规模.接着,介绍了一种以SDRAM为外部主存,以SRAM为外部缓存和以FPGA内部SRAM资源作为内部高速缓存的存储机制.然后,介绍了该存储机制的实现方法以及测试方法.最后对该三维图像重建系统的数据吞吐能力进行了测试,并将之与FDK算法所需的数据传输量进行了对比分析.试验结果表明:该存储机制的数据连续存取速度为151.9MB/s,数据随机存取速度为100MB/s,基本满足小规模的三维图像重建的数据存储与传输带宽的要求.
為瞭實現三維錐束CT圖像重建加速繫統的小型化,建立瞭基于FPGA的三維圖像重建繫統.併對該繫統中所採用的FDK重建算法所需的數據存儲量和數據傳輸量以及由SDRAM、SRAM和FPGA內部緩存組成的存儲繫統的數據吞吐率進行瞭研究.首先,根據FDK算法的濾波與反投影兩箇步驟介紹瞭三維錐束CT圖像重建繫統的數據規模.接著,介紹瞭一種以SDRAM為外部主存,以SRAM為外部緩存和以FPGA內部SRAM資源作為內部高速緩存的存儲機製.然後,介紹瞭該存儲機製的實現方法以及測試方法.最後對該三維圖像重建繫統的數據吞吐能力進行瞭測試,併將之與FDK算法所需的數據傳輸量進行瞭對比分析.試驗結果錶明:該存儲機製的數據連續存取速度為151.9MB/s,數據隨機存取速度為100MB/s,基本滿足小規模的三維圖像重建的數據存儲與傳輸帶寬的要求.
위료실현삼유추속CT도상중건가속계통적소형화,건립료기우FPGA적삼유도상중건계통.병대해계통중소채용적FDK중건산법소수적수거존저량화수거전수량이급유SDRAM、SRAM화FPGA내부완존조성적존저계통적수거탄토솔진행료연구.수선,근거FDK산법적려파여반투영량개보취개소료삼유추속CT도상중건계통적수거규모.접착,개소료일충이SDRAM위외부주존,이SRAM위외부완존화이FPGA내부SRAM자원작위내부고속완존적존저궤제.연후,개소료해존저궤제적실현방법이급측시방법.최후대해삼유도상중건계통적수거탄토능력진행료측시,병장지여FDK산법소수적수거전수량진행료대비분석.시험결과표명:해존저궤제적수거련속존취속도위151.9MB/s,수거수궤존취속도위100MB/s,기본만족소규모적삼유도상중건적수거존저여전수대관적요구.
In order to realize the miniaturization of three-dimensional cone-beam CT image reconstruction system to small-scale,A three-dimensional image reconstruction system based on FPGA is established.The memory bandwidth requirement of the FDK reconstruction algorithms and the data throughput of the storage system which is composed of SDRAM,SRAM and the internal R AM resource of FPGA is introduced.First,based on filtering algorithms and back projection algorithms the memory bandwidth requirement of a three-dimensional cone-beam CT image reconstruction system is studied.Then,a data access scheme is presented,which uses a SDRAM chip as its main storage a SRAM chip as its external cache and the SR AM resources of FPGA as its internal cache.Then,the process of the implementation and the testing methods of the storage scheme is introduced.Finally,data access capacity of the three-dimensional image reconstruction system was tested.Experimental results indicate that:the storage system can achieve a sequential access data rate of 151.9MB/s and a random access data rate of 100MB/s.It can satisfy the memory bandwidth requirement of a small-scale three-dimensional image reconstruction system.
