CAJ | 학술논문

针对SoC的高可靠性和低功耗的设计要求,分析了动态电压与频率调节技术对系统功耗、温度和软错误率的影响,构建了SoC的可靠性和功耗的协同优化设计模型,提出了可靠性和低功耗协同设计的新方法,并通过考虑可靠性的动态电压与频率调节调度算法进行了仿真,验证了算法的有效性和可行性.结果表明,在可靠性降低5%的情况下,可节省约15.99%的功耗.
침대SoC적고가고성화저공모적설계요구,분석료동태전압여빈솔조절기술대계통공모、온도화연착오솔적영향,구건료SoC적가고성화공모적협동우화설계모형,제출료가고성화저공모협동설계적신방법,병통과고필가고성적동태전압여빈솔조절조도산법진행료방진,험증료산법적유효성화가행성.결과표명,재가고성강저5%적정황하,가절성약15.99%적공모.
Tradeoff between the high reliability and low power consumption for SoC(system on a chip)Was investigated.Based on the proposed reliability and power consumption characterization model,reliability-aware and low-power design Was illustrated as a design methodology to balance reliability enhancement and power reduction.Reliability-aware dynamic voltage/frequency scheduling (DVFS)algorithm Was demonstrated as a case study of this new design methodology.The simulation demonstrates the effectiveness and feasibility of the methodology and obtains a significant improvement of 15.99%in energy consumption at a cost of 5%reliability decrease.