CAJ | 학술논문

文章针对FPGA与DSP之间的总线协议,建立FPGA与DSP总线通信的接口框架,根据不同类型的DSP设计相应的时序协调电路,保证DSP与外部器件之间高速稳定的数据通信。使用该设计方法在Quartus Ⅱ进行仿真,时序满足DSP的读写时序要求。实验证明该方法满足实际使用要求。
문장침대FPGA여DSP지간적총선협의,건립FPGA여DSP총선통신적접구광가,근거불동류형적DSP설계상응적시서협조전로,보증DSP여외부기건지간고속은정적수거통신。사용해설계방법재Quartus Ⅱ진행방진,시서만족DSP적독사시서요구。실험증명해방법만족실제사용요구。
The bus interface frame is built in the FPGA,and the time-sequence harmonized circuit is designed according to different object which is accessed by the DSP,which ensure that the DSP could access outer bus interface with highest speed.Finally,simulations are done,which indicate that the time-sequence is satisfied with the DSP demand,and the time margin is enough to the requirement of application.