CAJ | 학술논문

设计了一种用于超高速A/D转换器的脉宽调整电路.以基准输出电压为参照,利用差动放大器输出控制时钟输出占空比,最高可工作在1.7 GHz时钟频率下,锁定精度为50%±1%;拥有20%～80%占空比输入,且能很好地抑制时钟抖动.电路采用0.18 μm工艺制作,芯片面积为0.3 mm×0.1 mm,在1.9 V电源电压下,功耗小于40 mW.
설계료일충용우초고속A/D전환기적맥관조정전로.이기준수출전압위삼조,이용차동방대기수출공제시종수출점공비,최고가공작재1.7 GHz시종빈솔하,쇄정정도위50%±1%;옹유20%～80%점공비수입,차능흔호지억제시종두동.전로채용0.18 μm공예제작,심편면적위0.3 mm×0.1 mm,재1.9 V전원전압하,공모소우40 mW.
A high-speed pulse width control circuit was designed for high-speed A/D converter, in which differential dynamic amplifier output was used to control duty cycle of clock, with output voltage as reference. Operating at 1.7 GHz, this circuit can fast lock duty cycle at 50%±1% and work at 20% - 80% of duty cycle input, and further more, it can also suppress clock jitter. Fabricated in 0.18 μm CMOS process, the device occupies a chip area of 0.3 mm × 0.1 mm, and consumes less than 40 mW of power from a single 1.9 V supply.