计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2009年
15期
277-279
,共3页
芯片级多线程%调度%多核
芯片級多線程%調度%多覈
심편급다선정%조도%다핵
Chip Muiti-Threaded(CMT)%schedule%multi-core
随着芯片级多线程(CMT)处理器体系结构的迅速发展,操作系统必须采用新型CMT调度,以发挥其体系结构的性能优势.分析CMT调度面临的问题,通过扩展调度域的层次和结构支持CMT处理器内部的负载均衡,利用协同调度避免cache抖动等问题.采用效率、效率瓦特比和公平性等多种指标对操作系统进行性能评价,证明其性能得到优化.
隨著芯片級多線程(CMT)處理器體繫結構的迅速髮展,操作繫統必鬚採用新型CMT調度,以髮揮其體繫結構的性能優勢.分析CMT調度麵臨的問題,通過擴展調度域的層次和結構支持CMT處理器內部的負載均衡,利用協同調度避免cache抖動等問題.採用效率、效率瓦特比和公平性等多種指標對操作繫統進行性能評價,證明其性能得到優化.
수착심편급다선정(CMT)처리기체계결구적신속발전,조작계통필수채용신형CMT조도,이발휘기체계결구적성능우세.분석CMT조도면림적문제,통과확전조도역적층차화결구지지CMT처리기내부적부재균형,이용협동조도피면cache두동등문제.채용효솔、효솔와특비화공평성등다충지표대조작계통진행성능평개,증명기성능득도우화.
With the development of Chip Multi-Threaded(CMT) processor architecture, operating system must adopt an innovational CMT schedule algorithm to exert the advantage of performance for CMT processor architecture. This paper analyzes the problems of the CMT schedule. It extends the hierarchy and structure of scheduling domain to sustain the inner load of a CMT processor, imposes co-schedule to avoid cache thrashing. Operating system uses various standards evaluating performance, such as efficiency, and ratio of efficiency to watt, fairness and proves performance of system has optimized.