半导体技术
半導體技術
반도체기술
SEMICONDUCTOR TECHNOLOGY
2011年
12期
953-956
,共4页
徐壮%俞慧月%张辉%林霞
徐壯%俞慧月%張輝%林霞
서장%유혜월%장휘%림하
时钟发生器%锁相环%低功耗%低抖动%环形振荡器
時鐘髮生器%鎖相環%低功耗%低抖動%環形振盪器
시종발생기%쇄상배%저공모%저두동%배형진탕기
clock generator%phase-locked-loop%low consumption%low jitter%ring oscillator
基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现.电路使用1.2V单一电源电压,并在片上集成了环路滤波器.其中,振荡器为电流控制、全差分结构的五级环形振荡器.该信号发生器可以产生的时钟频率范围为12.5 ～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk =75 ps,ms =8.6 ps；Cycle-to-Cycle抖动为:pk-pk =132 ps,rms=14.1 ps.电路的面积为84 μm2.
基于整數分頻鎖相環結構實現的時鐘髮生器,該時鐘髮生器採用低功耗、低抖動技術,在SMIC 65 nm CMOS工藝上實現.電路使用1.2V單一電源電壓,併在片上集成瞭環路濾波器.其中,振盪器為電流控製、全差分結構的五級環形振盪器.該信號髮生器可以產生的時鐘頻率範圍為12.5 ～800MHz,工作在800 MHz時所需的功耗為1.54 mW,輸齣時鐘的週期抖動為:pk-pk =75 ps,ms =8.6 ps；Cycle-to-Cycle抖動為:pk-pk =132 ps,rms=14.1 ps.電路的麵積為84 μm2.
기우정수분빈쇄상배결구실현적시종발생기,해시종발생기채용저공모、저두동기술,재SMIC 65 nm CMOS공예상실현.전로사용1.2V단일전원전압,병재편상집성료배로려파기.기중,진탕기위전류공제、전차분결구적오급배형진탕기.해신호발생기가이산생적시종빈솔범위위12.5 ～800MHz,공작재800 MHz시소수적공모위1.54 mW,수출시종적주기두동위:pk-pk =75 ps,ms =8.6 ps；Cycle-to-Cycle두동위:pk-pk =132 ps,rms=14.1 ps.전로적면적위84 μm2.
This phase-locked-loop clock generator is based on SMIC 65 nm CMOS process,which focuses on low power and low jitter design.The generator is droved by 1.2 V single power supply and the loop filter is integrated on the chip.A full differential ring-oscillator consisted of five delay cells is used to generate 100-800 MHz clock,and output frequency range is 12.5 -800 MHz.The power consumption is 1.54 mW at 800 MHz.The period jitter (pk-pk) is 75 ps and period jitter (rms) is 8.6 ps; the cycle-to-cycle jitter (pk-pk) is 132 ps and cycle-to-cycle (rms) is 14.1 ps.The area of the circuit is 84 μm2.
