高技术通讯
高技術通訊
고기술통신
HIGH TECHNOLOGY LETTERS
2010年
1期
82-88
,共7页
VSR5%转换芯片%帧同步%通道对齐%12-16路映射
VSR5%轉換芯片%幀同步%通道對齊%12-16路映射
VSR5%전환심편%정동보%통도대제%12-16로영사
VSR5%converter IC%frame synchronization%channel deskew%12/16 conversion
给出了符合OIF-VSR5规范的40Gbps甚短距离光传输系统接收电路的设计与实现.该接收电路实现简单,由一片转换芯片及光接收模块构成.其特点是充分利用现场可编程门阵列(FPGA)内嵌的高速收发器成功实现了16×2.488Gbps和12×3.318Gbps信号的发送和接收,并且在一片FPGA上实现了诸如时钟数据恢复、串/并转换、帧同步、通道对齐、12-16路映射等全部功能.基于二分查找法的帧同步电路则大大提高了转换芯片的工作速度.Signaltap II逻辑分析仪的测试结果表明接收电路工作正常,性能良好.在此基础上,给出了VSR5实验系统的点到点测试方法,通过12通道垂直腔面发射激光器并行接收模块和7m 12芯多模带状光纤,将发送电路与接收电路相连,实现了OC768/STM-256 40Gbps的点到点测试,测试结果表明系统误码率小于10-12.
給齣瞭符閤OIF-VSR5規範的40Gbps甚短距離光傳輸繫統接收電路的設計與實現.該接收電路實現簡單,由一片轉換芯片及光接收模塊構成.其特點是充分利用現場可編程門陣列(FPGA)內嵌的高速收髮器成功實現瞭16×2.488Gbps和12×3.318Gbps信號的髮送和接收,併且在一片FPGA上實現瞭諸如時鐘數據恢複、串/併轉換、幀同步、通道對齊、12-16路映射等全部功能.基于二分查找法的幀同步電路則大大提高瞭轉換芯片的工作速度.Signaltap II邏輯分析儀的測試結果錶明接收電路工作正常,性能良好.在此基礎上,給齣瞭VSR5實驗繫統的點到點測試方法,通過12通道垂直腔麵髮射激光器併行接收模塊和7m 12芯多模帶狀光纖,將髮送電路與接收電路相連,實現瞭OC768/STM-256 40Gbps的點到點測試,測試結果錶明繫統誤碼率小于10-12.
급출료부합OIF-VSR5규범적40Gbps심단거리광전수계통접수전로적설계여실현.해접수전로실현간단,유일편전환심편급광접수모괴구성.기특점시충분이용현장가편정문진렬(FPGA)내감적고속수발기성공실현료16×2.488Gbps화12×3.318Gbps신호적발송화접수,병차재일편FPGA상실현료제여시종수거회복、천/병전환、정동보、통도대제、12-16로영사등전부공능.기우이분사조법적정동보전로칙대대제고료전환심편적공작속도.Signaltap II라집분석의적측시결과표명접수전로공작정상,성능량호.재차기출상,급출료VSR5실험계통적점도점측시방법,통과12통도수직강면발사격광기병행접수모괴화7m 12심다모대상광섬,장발송전로여접수전로상련,실현료OC768/STM-256 40Gbps적점도점측시,측시결과표명계통오마솔소우10-12.
The paper presents the receiver design and realization of a 40Gbps very short reach (VSR) optical transmission system compatible for the OIF-VSR5 specification. The receiver consists of a converter IC and an optical receiver module, characterized by making full use of high speed transceivers in the field-programmable gate array (FPGA) to successfully realize 16×2.488 Gbps and 12×3.318Gbps signal transmission and reception. All of the functions of the converter IC such as clock data recovery, serial/parallel conversion, frame synchronization, channel deskew, 12/16 conversion and channel rearrangement are implemented in one FPGA chip.The frame synchronization logic based on the binary search algorithm can speed up the converter IC greatly. Testing results obtained from Signaltap II indicate that the circuit works well and correctly. Furthermore, this paper presents a point-to-point test of the VSR5 experiment system. By connecting transmitter and receiver through 7-meter 12-fiber multi-model ribbon, a SDH STM-256/OC768 40Gbps point-to-point test was realized, and a low bit error rate of 10-12 was obtained.