CAJ | 학술논문

针对传统的Smith-Waterman硬件算法加速器未保存回溯路径而无法回溯的问题,通过将计算路径存入外存,在FPGA平台上基于脉动阵列实现了带回溯的Smith-Waterman算法加速器,详细阐述了算法加速器回溯设计中的关键技术以及算法加速器的系统结构.实验表明,与传统的解决方案相比,带回溯的算法加速器最高可获得161倍加速比,能够有效提高带回溯的Smith-Waterman算法执行效率.
침대전통적Smith-Waterman경건산법가속기미보존회소로경이무법회소적문제,통과장계산로경존입외존,재FPGA평태상기우맥동진렬실현료대회소적Smith-Waterman산법가속기,상세천술료산법가속기회소설계중적관건기술이급산법가속기적계통결구.실험표명,여전통적해결방안상비,대회소적산법가속기최고가획득161배가속비,능구유효제고대회소적Smith-Waterman산법집행효솔.
The Smith-Waterman algorithm accelerator with backtracking, which has not been implemented in hardware before, is designed and implemented on FPGA platform with systolic array by storing the path data into DRAM. The key techniques of backtracking design and the architecture of algorithm accelerator are discussed in detail. Compared with the conventional scheme, the FPGA-based accelerator with backtracking is more effective, with the acceleration reaching 161.