一种12位50 MSPS流水线逐次逼近A/D转换器
일충12위50 MSPS류수선축차핍근A/D전환기
A 12-Bit 50 MSPS Pipelined Successive Approximation A/D Converter with Two-Phase Non-Overlapping Clock and Double SHA
  • 万方数据
    微电子学 미전자학
    MICROELECTRONICS
    2010年 2期 190-194 ,共5页

    董磊%涂志娣%王百鸣%阳广%薛超杰%刘浩瑞

    동뢰%도지제%왕백명%양엄%설초걸%류호서

    A/D转换器%双SHA结构%非交叠时钟 A/D轉換器%雙SHA結構%非交疊時鐘
    A/D전환기%쌍SHA결구%비교첩시종
    A/D converter%Double SHA structure%Non-overlapping clock
    提出了一种两相非交叠时钟双SHA结构的12位50 MSPS流水线逐次逼近A/D转换器.电路在OrCAD/PSpice10.5平台上进行仿真和测试.结果表明,该A/D转换器最高采样速率为50 MSPS.在0.05 MHz和0.10 MHz信号输入下,有效位数分别为11.4位和10.7位;在2.00 MHz和4.00 MHz下,有效位数分别为7.4位和7.1位.给出了A/D转换器的总体结构和模块结构,以及测试波形和动态测试结果.
    제출료일충량상비교첩시종쌍SHA결구적12위50 MSPS류수선축차핍근A/D전환기.전로재OrCAD/PSpice10.5평태상진행방진화측시.결과표명,해A/D전환기최고채양속솔위50 MSPS.재0.05 MHz화0.10 MHz신호수입하,유효위수분별위11.4위화10.7위;재2.00 MHz화4.00 MHz하,유효위수분별위7.4위화7.1위.급출료A/D전환기적총체결구화모괴결구,이급측시파형화동태측시결과.
    A 12-bit 50 MSPS A/D converter with two-phase non-overlapping clock and double SHA was designed. The circuit was simulated and tested in OrCAD/PSpice10.5 platform. Results showed that the A/D converter had a maximum sampling rate of 50 MSPS, ENOB of 11.4 bits and 10.7 bits at 0.05 MHz and 0.10 MHz input signals, and 7.4 bits and 7.1 bits at 2.00 MHz and 4.00 MHz input signals, respectively. The framework of the A/D converter and its module structure were described, and test waveforms and dynamic results were also discussed.
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