微型机与应用
微型機與應用
미형궤여응용
MICROCOMPUTER & ITS APPLICATIONS
2014年
11期
56-60
,共5页
半速率时钟结构%解复用%CMOS%电流模式逻辑%锁存器
半速率時鐘結構%解複用%CMOS%電流模式邏輯%鎖存器
반속솔시종결구%해복용%CMOS%전류모식라집%쇄존기
half-rate clock architecture%demultiplexer%CMOS%CML%latch
采用 SMIC 0.18μm CMOS 工艺,设计了高速收发器中双模1∶8/1∶10解复用电路。解复用电路采用半速率结构,基于电流模式逻辑完成对2.5 Gb/s 差分数据1∶2解复用电路;基于交替反相的锁存器和反馈逻辑完成双模4/5时钟分频和占空比调节;通过适当的相位控制实现了由相位控制链、交替存储链和同步输出链构成的1∶4/1∶5模式可选的数字CMOS解复用电路;1∶2与1∶4/1∶5解复用级联完成1∶8/1∶10串并转换。采用数模混合仿真方法对电路进行仿真,结果表明该电路能可靠工作。
採用 SMIC 0.18μm CMOS 工藝,設計瞭高速收髮器中雙模1∶8/1∶10解複用電路。解複用電路採用半速率結構,基于電流模式邏輯完成對2.5 Gb/s 差分數據1∶2解複用電路;基于交替反相的鎖存器和反饋邏輯完成雙模4/5時鐘分頻和佔空比調節;通過適噹的相位控製實現瞭由相位控製鏈、交替存儲鏈和同步輸齣鏈構成的1∶4/1∶5模式可選的數字CMOS解複用電路;1∶2與1∶4/1∶5解複用級聯完成1∶8/1∶10串併轉換。採用數模混閤倣真方法對電路進行倣真,結果錶明該電路能可靠工作。
채용 SMIC 0.18μm CMOS 공예,설계료고속수발기중쌍모1∶8/1∶10해복용전로。해복용전로채용반속솔결구,기우전류모식라집완성대2.5 Gb/s 차분수거1∶2해복용전로;기우교체반상적쇄존기화반궤라집완성쌍모4/5시종분빈화점공비조절;통과괄당적상위공제실현료유상위공제련、교체존저련화동보수출련구성적1∶4/1∶5모식가선적수자CMOS해복용전로;1∶2여1∶4/1∶5해복용급련완성1∶8/1∶10천병전환。채용수모혼합방진방법대전로진행방진,결과표명해전로능가고공작。
A dual-mode 1∶8/1∶10 demultiplexing circuit used in high-speed transceiver is designed with SMIC 0.18μm CMOS technology. The demultiplexer is based on half-rate architecture, with 1∶2 demultiplexing for 2.5 Gb/s differential data based on current mode logic, dual-mode 4/5 frequency division and duty-cycle adjustment based on alternate inversion latches. dual-mode 1∶4/1∶5 digital demultiplexer consisting of phase control chain, alternate sample chain and synchronous output chain with appropriate phase control. The 1∶2 and 1∶4/1∶5 demultiplexer cascade for 1∶8/1∶10 deserialization. The proposed circuit is verified with digital/analog mixed simulation method and the results show that the circuit can work reliably.