CAJ | 학술논문

Very shallow junctions for S/D extension in deep sub-micron CMOS devices are required to suppress the short channel effect as devices scaling down, and the surface concentrations (N,) of these junctions need to be kept in a higher value to reduce the series resistance of the lightly doped drain structure. But it is very difficult for the conventional ion implantation to meet the requirement above. This article presents the results of forming very shallow and ultrashallow junctions used in 0.25 micron and 0.10 micron CMOS devices respectively with low energy implantation (LEI) and pre-amorphization implantation plus low energy implantation (PAI+LEI). The LEI was performed on the modified normal ion-imptantor (IM-200M). Using LEI only the minimum junction depth,is 61nm for NMOS and 57nm for PMOS (Nsub=1×1018cm-3) respectively after 1000℃ RTA and both Ns are above 3×1019cm-3 While using Ge PAI+LEI,under the optimized processing condition,the junction depth of 58nm for NMOS and 42nm for PMOS are obtained,with the leakage current density being 4nA/cm2.