CAJ | 학술논문

利用截止频率为49GHz 的0.18-μm CMOS工艺,设计实现了11.6-GHz锁相环电路.该电路由模拟乘法鉴相器、单极点低通滤波器及采用可变负电阻负载的三级环形振荡器构成.在片晶圆测试表明,该芯片在输入速率为11.6 GHz、长度为231-1伪随机序列的情况下,恢复时钟的均方根抖动为2.2 ps.锁相环的跟踪范围为250 MHz.环形振荡器在偏离中心频率为10 MHz处的单边带相位噪声为-107 dBc/Hz.在锁定条件下,锁相环在偏离中心频率为10 MHz处的单边带相位噪声为-99dBc/Hz.芯片面积为0.47 mm×0.72 mm,在1.8-V电源供电下,功耗为164 mW.
이용절지빈솔위49GHz 적0.18-μm CMOS공예,설계실현료11.6-GHz쇄상배전로.해전로유모의승법감상기、단겁점저통려파기급채용가변부전조부재적삼급배형진탕기구성.재편정원측시표명,해심편재수입속솔위11.6 GHz、장도위231-1위수궤서렬적정황하,회복시종적균방근두동위2.2 ps.쇄상배적근종범위위250 MHz.배형진탕기재편리중심빈솔위10 MHz처적단변대상위조성위-107 dBc/Hz.재쇄정조건하,쇄상배재편리중심빈솔위10 MHz처적단변대상위조성위-99dBc/Hz.심편면적위0.47 mm×0.72 mm,재1.8-V전원공전하,공모위164 mW.
A design of a 11.6-GHz phase-locked loop (PLL) fabricated in 49-GHz 0.18-μm CMOS (complementary metal-oxide-semiconductor transistor) technology is described.An analog multiplier phase detector (PD),a one-pole passive low pass filter and a three-stage ring oscillator with variable negative-resistance loads build up the monolithic phase-locked loop.The measured rms jitter of output signal via on-wafer testing is 2.2 ps under the stimulation of 231-1 bit-long pseudo random bit sequence (PRBS) at the bit rate of 11.6 GHz.And the tracking range is 250 MHz.The phase noise in the locked condition is measured to be -107 dBc/Hz at 10 MHz offset,and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset.The circuit area of the proposed PLL is only 0.47 mm×0.72 mm and the direct current (DC) power dissipation is 164 mW under a 1.8-V supply.