CAJ | 학술논문

实现了一种高速的IDEA(International Data Encryption Algorithm)加密模块。首先，在分析IDEA算法的基本运算模块的基础上，重新安排了IDEA算法的各个子模块，采用8级流水线结构。其次，对IDEA算法实现速度影响最大的模乘部分，提出了一种新的保留进位模加器(MCSA)的费马数模乘结构，同时，对IDEA芯片的输入输出部分，针对高速和安全性两方面的需要作了合理考虑。最后，在对各子模块分别验证后，在一块FPGA上对整个加密算法进行了验证。理论分析和仿真的结果表明，该结构能实现速度和面积上较优的权衡。
실현료일충고속적IDEA(International Data Encryption Algorithm)가밀모괴。수선，재분석IDEA산법적기본운산모괴적기출상，중신안배료IDEA산법적각개자모괴，채용8급류수선결구。기차，대IDEA산법실현속도영향최대적모승부분，제출료일충신적보류진위모가기(MCSA)적비마수모승결구，동시，대IDEA심편적수입수출부분，침대고속화안전성량방면적수요작료합리고필。최후，재대각자모괴분별험증후，재일괴FPGA상대정개가밀산법진행료험증。이론분석화방진적결과표명，해결구능실현속도화면적상교우적권형。
Implementation of a high performance IDEA (International Data Encryption Algorithm) module is described in the paper. Firstly, based on the analysis of basic building blocks, the structure of IDEA is rearranged with eight pipelines. Secondly, as the multiplication modulo, a Fermat Prime, is the critical path of the IDEA, a new VLSI architecture for the dedicated multiplication based on MCSA (modular carried saved adder) is presented. At the same time, an I/O interface is designed, with speed and security taken into consideration. Finally, after the verification of the submodules, the IDEA is implemented on a single FPGA. Results from both theoretical analysis and simulation show that the dedicated structure is a good trade-off between speed and area.