CAJ | 학술논문

设计了一种用于逐次逼近型模数转换器中的比较器失调和电容失配自校准电路.通过增加校准周期,该电容自校准结构即可与原电路并行工作,实现高精度与低功耗.校准精度可达14bit.采用该电路设计了一个用于逐次逼近型结构的10bit 3Msps模数转换器单元,该芯片在SMIC 0.18μm 1.8V工艺上实现,总的芯片面积为0.25mm2.芯片实测,在采样频率为1.8MHz,输入320kHz正弦波时,信号噪声失真比为55.9068dB,无杂散动态范围为64.5767dB,总谐波失真为-74.8889dB,功耗为3.1mW.
설계료일충용우축차핍근형모수전환기중적비교기실조화전용실배자교준전로.통과증가교준주기,해전용자교준결구즉가여원전로병행공작,실현고정도여저공모.교준정도가체14bit.채용해전로설계료일개용우축차핍근형결구적10bit 3Msps모수전환기단원,해심편재SMIC 0.18μm 1.8V공예상실현,총적심편면적위0.25mm2.심편실측,재채양빈솔위1.8MHz,수입320kHz정현파시,신호조성실진비위55.9068dB,무잡산동태범위위64.5767dB,총해파실진위-74.8889dB,공모위3.1mW.
Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0.18μm 1.8V process and occupies 0.25mm2. It consumes 3.1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is -74. 8889dB when sampling a 320kHz sine wave.