CAJ | 학술논문

设计基于SoPC技术的嵌入式数字频率计实现方案.该方案以Altera公司的EP1C6芯片作为设计载体, 将IP软核、NiosⅡCPU等功能模块嵌入其中, 采用硬件语言描述、参数选择配置、功能裁剪定制等多种设计方式和软硬件协同开发手段, 在单片FPGA上构建了整个测频系统硬件, 具有精度高、功耗小、成本低、体小便携、工作可靠、开发效率高等特点, 是嵌入式应用系统设计的一次有益尝试.文中详细阐述了利用集成开发平台QuartusⅡ进行系统硬件设计和软件调试的思路与过程.
설계기우SoPC기술적감입식수자빈솔계실현방안.해방안이Altera공사적EP1C6심편작위설계재체, 장IP연핵、NiosⅡCPU등공능모괴감입기중, 채용경건어언묘술、삼수선택배치、공능재전정제등다충설계방식화연경건협동개발수단, 재단편FPGA상구건료정개측빈계통경건, 구유정도고、공모소、성본저、체소편휴、공작가고、개발효솔고등특점, 시감입식응용계통설계적일차유익상시.문중상세천술료이용집성개발평태QuartusⅡ진행계통경건설계화연건조시적사로여과정.
The design and implementation of a embedded digital cymometer based on SoPC is introduced. Altera's EP1C6 device is used as design carrier in this project, functional modules like soft IP core and NiosⅡ CPU are embedded. Multi-manner such as hardware language description, preferences, function customization and cooperating exploi-tation are used in this design. Entire system hardware is constructed on single-chip FPGA, it has the feature of high precision, low power, low cost consumption, miniaturization, reliable operation and high efficiency. A design of embedded system application is attempted. The thinking and the process, which use integrated development platform QuartusⅡ to perform system hardware design and software debugging, are explained in detail in the paper.