CAJ | 학술논문

采用TSMC 0.18μmCMOS工艺实现了一种应用于光纤通信系统SDH STM-64的10 Gbit/s1:4分接器,整个系统采用树型结构,由1个高速1:2分接器、2个低速1:2分接器、分频器以及数据和时钟输入输出缓冲组成.为达到优化性能、降低功耗的目标,其中高速分接部分和5 GHz 1:2分频器都采用共栅结构、单时钟输入的锁存器;而低速分接部分则由动态CMOS逻辑实现.通过在片晶圆测试,该芯片在输入10 Gbit/s、长度为231-1的伪随机码流时工作性能良好,电源电压1.8 V,功耗仅为100mW.芯片面积为0.65 mm×0.75 mm.
채용TSMC 0.18μmCMOS공예실현료일충응용우광섬통신계통SDH STM-64적10 Gbit/s1:4분접기,정개계통채용수형결구,유1개고속1:2분접기、2개저속1:2분접기、분빈기이급수거화시종수입수출완충조성.위체도우화성능、강저공모적목표,기중고속분접부분화5 GHz 1:2분빈기도채용공책결구、단시종수입적쇄존기;이저속분접부분칙유동태CMOS라집실현.통과재편정원측시,해심편재수입10 Gbit/s、장도위231-1적위수궤마류시공작성능량호,전원전압1.8 V,공모부위100mW.심편면적위0.65 mm×0.75 mm.
A 10 Gbit/s 1: 4 demultiplexer(DEMUX) fabricated in 0. 18 μm CMOS (complementary metal-oxidesemiconductor transistor) technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1: 2 DEMUX, two low-speed 1: 2 DEMUXs, a divider, and input and output buffers for data and clock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1: 2 DEMUX and the 5 GHz 1: 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed 1: 2 DEMUXs. Measured results at 10 Gbit/s by 231 - 1 pseudo random bit sequences (PRBS) via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.