CAJ | 학술논문

提出了一种新型的通用低压轨至轨CMOS运放.该运放在整个输入共模电压范围内获得了恒定的跨导、摆率和恒定的高增益.所提出的电路有应用于深亚微米工艺的潜力,因为运放电路的运行不依赖于晶体管平方率或线性率的约束.因此该电路比较紧凑,适用于VLSI单元的应用.轨至轨CMos运放采用DPDM CMOS混合信号工艺设计,模拟结果表明在整个输入共模电压范围内,跨导、摆率和增益的波动分别为1%,2.3%和1.36dB.在此基础上进行了版图设计和流片测试,版图面积为0.072 mm2,实际测试结果与模拟结果基本一致.
제출료일충신형적통용저압궤지궤CMOS운방.해운방재정개수입공모전압범위내획득료항정적과도、파솔화항정적고증익.소제출적전로유응용우심아미미공예적잠력,인위운방전로적운행불의뢰우정체관평방솔혹선성솔적약속.인차해전로비교긴주,괄용우VLSI단원적응용.궤지궤CMos운방채용DPDM CMOS혼합신호공예설계,모의결과표명재정개수입공모전압범위내,과도、파솔화증익적파동분별위1%,2.3%화1.36dB.재차기출상진행료판도설계화류편측시,판도면적위0.072 mm2,실제측시결과여모의결과기본일치.
A novel general-purpose low-voltage rail-to-rail CMOS(complementary metal-oxide-semiconductor transistor)operational amplifier(op-amp)is introduced, which obtainsconstant transconductance, slew rate and constant high gain overthe entire input common mode voltage range. The proposedscheme has the potential for applications in deep submicrometertechnology, as the operation of the circuit does not exclusivelyrely on the square-law or the linear-law of transistors. The schemeis compact and suitable for applications as VLSI cell. The rail-to-rail op-amp has been implemented in DPDM 0.6 um mixed-signal process. The simulations show that in the entire range ofinput common mode voltage, the variations in transconductance,SR and gain are 1% ,2.3%, 1.36 dB, respectively. Based on this,the layout and tape-out are carried out. The area of layout is0.072 mm2. The test results are basically consistent with thecircuit simulation.