FDP FPGA芯片的设计实现
FDP FPGA심편적설계실현
Design and Implementation of an FDP Chip
  • 万方数据
    半导体学报 반도체학보
    CHINESE JOURNAL OF SEMICONDUCTORS
    2008年 4期 713-718 ,共6页

    陈利光%王亚斌%吴芳%来金梅%童家榕%张火文%屠睿%王建%王元%申秋实%余慧%黄均鼐%卢海舟%潘光华

    진리광%왕아빈%오방%래금매%동가용%장화문%도예%왕건%왕원%신추실%여혜%황균내%로해주%반광화

    FPGA%可编程逻辑块,可编程互联资源%开关盒 FPGA%可編程邏輯塊,可編程互聯資源%開關盒
    FPGA%가편정라집괴,가편정호련자원%개관합
    FPGA%programmable logic block%programmable routing resource: switch box
    研究了新型的FDP FPGA电路结构及其设计实现.新颖的基于3输入查找表的可编程单元结构,与传统的基于4输入查找表相比,可以提高约11%的逻辑利用率;独特的层次化的分段可编程互联结构以及高效的开关盒设计,使得不同的互联资源可以快速直接相连,大大提高了可编程布线资源效率.FDP芯片包括1600个可编程逻辑单元、160个可用IO、内嵌16k双开块RAM,采用SMIC 0.18μm CMOS工艺全定制方法设计并流片,其裸芯片面积为6.104mm×6.620mm.最终芯片软硬件测试结果表明:芯片各种可编程资源可以高效地配合其软件正确实现用户电路功能.
    연구료신형적FDP FPGA전로결구급기설계실현.신영적기우3수입사조표적가편정단원결구,여전통적기우4수입사조표상비,가이제고약11%적라집이용솔;독특적층차화적분단가편정호련결구이급고효적개관합설계,사득불동적호련자원가이쾌속직접상련,대대제고료가편정포선자원효솔.FDP심편포괄1600개가편정라집단원、160개가용IO、내감16k쌍개괴RAM,채용SMIC 0.18μm CMOS공예전정제방법설계병류편,기라심편면적위6.104mm×6.620mm.최종심편연경건측시결과표명:심편각충가편정자원가이고효지배합기연건정학실현용호전로공능.
    A novel Fudan programmable logic chip (FDP) was designed and implemented with a SMIC 0.18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O,and 16kbit dual port block RAM. Its die size is 6.104ram × 6.620mm,with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.
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