CAJ | 학술논문

为了利用片上缓冲技术来提高处理器应用性能,提出一种面向写穿透Cache的写合并设计方法.使用同步动态随机存储器(SDRAM)的单个写方式和片上写缓冲器,对SDRAM一行内的局部数据采用写合并策略,由此提高了外部存储的访问效率,同时给出了连续和单个Cache读写的缓存与内存的数据一致性策略.在寄存器传输语言(RTL)仿真环境下使用mp3解码对Leon2处理器进行数据测试,结果表明:在缓冲区优化为3行8列的参数下,SDRAM每次行开启平均进行7.8个字的写入操作,外存的读写效率由12%提高到19%;在TSMC 0.18μm工艺下,综合后面积为0.263 mm~2,流片后工作主频为100 MHz.
위료이용편상완충기술래제고처리기응용성능,제출일충면향사천투Cache적사합병설계방법.사용동보동태수궤존저기(SDRAM)적단개사방식화편상사완충기,대SDRAM일행내적국부수거채용사합병책략,유차제고료외부존저적방문효솔,동시급출료련속화단개Cache독사적완존여내존적수거일치성책략.재기존기전수어언(RTL)방진배경하사용mp3해마대Leon2처리기진행수거측시,결과표명:재완충구우화위3행8렬적삼수하,SDRAM매차행개계평균진행7.8개자적사입조작,외존적독사효솔유12%제고도19%;재TSMC 0.18μm공예하,종합후면적위0.263 mm~2,류편후공작주빈위100 MHz.
A write coalescing design for write-through cache is proposed to promote the performance of application processors using on-chip buffer. The scheme of write coalition for the local data in the same row of SDRAM (synchronous dynamic random access memory) is designed to improve accessing efficiency by employing the single write mode of SDRAM and on-chip buffer. A coherence scheme for the single or multiple cache data reading or writing is also presented. Simulation for mp3 decoding data is implemented in the RTL (register transmit language) simulation environment for Leon2 processor. The simulation results show that when the on-chip buffers are optimized at 3 rows and 8 columns, average 7. 8 words are written into the SDRAM after every row pre-charge, and the accessing efficiency increases from 12% to 19% at 100 MHz, and that the area of the proposed design is 0. 263 mm~2 under TSMC 0. 18 μm process.