CAJ | 학술논문

首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为+0.31/-0.46LSB,差分非线性为+0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.
수선대용우CMOS저중빈GPS접수궤적모수전환기(ADC)진행료설계고필.유ADC인입적신조비강저여사개인소유관:중빈대관,채양솔,ADC적비특수급ADC적최대역치여조성균방근비치.재설계고필적기출상,채용TSMC 0.25tan CMOS단층다정규오층금속공예실현료일개4 bit 16.368 MHz섬삭형모수전환기,병장중점방재료전치방대기화제출적신적비교기적설계화우화상.재시종채양솔16.368 MHz화수입신호빈솔4.092 MHz적조건하,전환기측시득도적신조실진비위24.7 dB,무잡산동태범위위32.1 dB,적분비선성위+0.31/-0.46LSB,차분비선성위+0.66/-0.46LSB,공모위3.5mW.ADC점용심편면적0.07 mm2.
The design considerations of an analog-to-digital converter (ADC) for a CMOS Low-IF GPS re- ceiver are described first. Signal-to-noise degradation due to ADC is dependent on four factors: the IF bandwidth, the sampling rate, the number of bits of the ADC, and the ratio of the maximum ADC thresh-old to the root-mean-square noise level. Then based on the design considerations, a 4 bit 16. 368 MHz Flash ADC is implemented using TSMC 0. 25/μm CMOS single-poly five-metal process and the special at-tention is spent on the design and optimization of the preamplifier and proposed new comparator. The con-verter achieves a peak signal-to-noise-and-distortion ratio of 24.7 dB, peak spurious-free dynamic range of 32.1 dB, integral nonlinearity of +0. 31/-0. 46LSB, integral nonlinearity of +0.66/-0.46LSB, and a pow-er of 3.5 mW at 16.368 MHz clock and fin=4. 092 MHz. The converter occupies 0.07 mm2 of chip area.