计算机科学技术学报（英文版）
計算機科學技術學報（英文版）
계산궤과학기술학보（영문판）
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
2005年
2期
237-242
,共6页
CMOS%flip-flops%multiple-valued clock%multiple-valued logic
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. Pspice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
