微电子学
微電子學
미전자학
MICROELECTRONICS
2010年
2期
199-203
,共5页
徐鸣远%周述涛%朱璨%沈晓峰
徐鳴遠%週述濤%硃璨%瀋曉峰
서명원%주술도%주찬%침효봉
半并行%A/D转换器%自动校零%迟滞比较器
半併行%A/D轉換器%自動校零%遲滯比較器
반병행%A/D전환기%자동교령%지체비교기
Half-flash%A/D converter%Auto-zero%Hysteretic comparator
简要介绍了半并行结构的A/D转换器原理.针对该结构的A/D转换器,提出了一种能自动校零、迟滞、全差分输入及多级前置放大的比较器.解决了输入失调电压、噪声环境下单转换、电荷注入、带宽、转换速度等问题.给出了应用该比较器的0.6 μm CMOS半并行A/D转换器的性能.结果表明,设计的比较器能使半并行ADC的DNL和INL小于±0.5 LSB,SNR大于48 dB.
簡要介紹瞭半併行結構的A/D轉換器原理.針對該結構的A/D轉換器,提齣瞭一種能自動校零、遲滯、全差分輸入及多級前置放大的比較器.解決瞭輸入失調電壓、譟聲環境下單轉換、電荷註入、帶寬、轉換速度等問題.給齣瞭應用該比較器的0.6 μm CMOS半併行A/D轉換器的性能.結果錶明,設計的比較器能使半併行ADC的DNL和INL小于±0.5 LSB,SNR大于48 dB.
간요개소료반병행결구적A/D전환기원리.침대해결구적A/D전환기,제출료일충능자동교령、지체、전차분수입급다급전치방대적비교기.해결료수입실조전압、조성배경하단전환、전하주입、대관、전환속도등문제.급출료응용해비교기적0.6 μm CMOS반병행A/D전환기적성능.결과표명,설계적비교기능사반병행ADC적DNL화INL소우±0.5 LSB,SNR대우48 dB.
Theory of operation of A/D converter with half-flash structure was described. A multi-stage pre-amp comparator with auto-zero, hysteresis and fully differential input was proposed for half-flash A/D converter. Problems of input offset voltage, single conversion in noise environment, charge injection, bandwidth and conversion rate were solved. A half-flash A/D converter was fabricated in 0.6 μm CMOS process. Test results showed that the A/D converter had a DNL/INL less than ±0.5 LSB and an SNR more than 48 dB.
