CAJ | 학술논문

提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%.
제출료일충우화시연적증량식포국산법,해산법근거시연분석적결과재질대구해적과정중동태조정선망권치.재차기출상,제출료삼충동시우화시연화옹제도적다목표우화적포국산법,재만족시연화옹제도약속적전제하대관건로경상적단원진행위치조정.실험결과표명해산법능구유효지제고심편속도병강저주선옹제.대우우화선장득도적포국방안,최장로경상적시연치재증량식포국지후능구강저10%.
A new approach of incremental placement approach is described.The obtained timing information drives an efficient net-based placement technique,which dynamically adapts the net weights during successive placement steps.Several methods to combine timing optimization and congestion reducing together are proposed.Cells on critical paths are replaced according to timing and congestion constraints.Experimental results show that our approach can efficiently reduce cycle time and enhance route ability.The max path delay is reduced by 10% on an average after incremental placement on wirelength-optimized circuits.And it achieves the same quality with a high speed up compared to timing driven detailed placement algorithm.