电子与封装
電子與封裝
전자여봉장
EIECTRONICS AND PACKAGING
2011年
11期
18-21,32
,共5页
流水线ADC%栅压自举开关%增益增强型运算放大器%采样保持电路
流水線ADC%柵壓自舉開關%增益增彊型運算放大器%採樣保持電路
류수선ADC%책압자거개관%증익증강형운산방대기%채양보지전로
pipeline ADC%bootstrapped switch%gain-boosted operational amplifier%sample-and-hold circuit
介绍了一种应用于12位、10MS/s流水线模数转换器前端的高性能采样保持（SH）电路的设计。该电路采用全差分电容翻转型结构及下极板采样技术,有效地减少噪声、功耗及电荷注入误差。采用一种改进的栅源电压恒定的自举开关,极大地减小电路的非线性失真。运算放大器为增益增强型折叠式共源共栅结构,能得到较高的带宽和直流增益。该采样保持电路采用JAZZ 0.6μm BiCMOS工艺来实现,在5V电源电压、10MHz采样频率下,当输入信号频率为1MHz时,仿真结果显示无杂散动态范围（SFDR）为107.82dB、信噪比（SNR）为87.8dB、总谐波失真比（THD）为-105.2dB。该部分电路版图面积为0.4mm×0.8mm,功耗仅为11mW。
介紹瞭一種應用于12位、10MS/s流水線模數轉換器前耑的高性能採樣保持（SH）電路的設計。該電路採用全差分電容翻轉型結構及下極闆採樣技術,有效地減少譟聲、功耗及電荷註入誤差。採用一種改進的柵源電壓恆定的自舉開關,極大地減小電路的非線性失真。運算放大器為增益增彊型摺疊式共源共柵結構,能得到較高的帶寬和直流增益。該採樣保持電路採用JAZZ 0.6μm BiCMOS工藝來實現,在5V電源電壓、10MHz採樣頻率下,噹輸入信號頻率為1MHz時,倣真結果顯示無雜散動態範圍（SFDR）為107.82dB、信譟比（SNR）為87.8dB、總諧波失真比（THD）為-105.2dB。該部分電路版圖麵積為0.4mm×0.8mm,功耗僅為11mW。
개소료일충응용우12위、10MS/s류수선모수전환기전단적고성능채양보지（SH）전로적설계。해전로채용전차분전용번전형결구급하겁판채양기술,유효지감소조성、공모급전하주입오차。채용일충개진적책원전압항정적자거개관,겁대지감소전로적비선성실진。운산방대기위증익증강형절첩식공원공책결구,능득도교고적대관화직류증익。해채양보지전로채용JAZZ 0.6μm BiCMOS공예래실현,재5V전원전압、10MHz채양빈솔하,당수입신호빈솔위1MHz시,방진결과현시무잡산동태범위（SFDR）위107.82dB、신조비（SNR）위87.8dB、총해파실진비（THD）위-105.2dB。해부분전로판도면적위0.4mm×0.8mm,공모부위11mW。
A high performance sample and hold（SH） circuit for use in the front end of a 12-bit 10MS/s Pipeline ADC is presented.The full differential capacitor flip-around architecture has been used to reduce both noise and power.To reduce the nonlinearity error cause by the sampling switch,a signal dependent clock bootstrapping system is used.A fully differential folded cascade operational amplifier is designed using a gain-boosted circuit to get high gain and wideband.It is implemented using 0.6μm BiCMOS process,and simulation results demonstrate that the S/H circuit consumes 11mW at 5V supply with a sampling rate of 10MHz.A 107.8dB spurious-free dynamic range（SFDR）,an 88.1dB signal and noise ratio（SNR）,and a-105.2dB total harmonic distortion（THD）are obtained.
