CAJ | 학술논문

三相Boost功率因数校正(Power Factor Correction, PFC)电路的分析和设计远比DC/DC变换器复杂，因为平均模型状态方程的系数矩阵是时变的。采用d-q变换后，稳态系数阵为常数，但由于d、q通道相互耦合，设计难度大。文中结合等效拓朴变换和功率平衡法，把主电路简化成DC/DC变换器，使主电路的阶次降为二。简化电路与原始电路的参数对应关系非常简单，可用于主电路参数设计，模型经小信号线性化之后，还可在复频域设计输出电压调节器。小信号模型使该类电路的设计大为简化。对比性的仿真结果说明简化模型能反映原电路的主要动态特性。
삼상Boost공솔인수교정(Power Factor Correction, PFC)전로적분석화설계원비DC/DC변환기복잡，인위평균모형상태방정적계수구진시시변적。채용d-q변환후，은태계수진위상수，단유우d、q통도상호우합，설계난도대。문중결합등효탁박변환화공솔평형법，파주전로간화성DC/DC변환기，사주전로적계차강위이。간화전로여원시전로적삼수대응관계비상간단，가용우주전로삼수설계，모형경소신호선성화지후，환가재복빈역설계수출전압조절기。소신호모형사해류전로적설계대위간화。대비성적방진결과설명간화모형능반영원전로적주요동태특성。
A reduced-order big-signal model of three-phase pulse-width-modulation (PWM) rectifiers is proposed. The analysis and design of the three-phase boost Power Factor Correction (PFC) circuit is far more complex than the dc-to-dc converter, in that the coefficient of the state equation are time-variant. Although they become constants when in steady state in d-q frame, it is difficult to design due to the couple of the d- and q-channel. By combination of the topology transformation and Tellegen's theorem, the mains can be simplified to a boost dc-to-dc converter, thus reduce the mains' order to two, and the parameter of the simplified circuit is deduced. The proposed model can also be linearized to obtain the small-signal model. The small-signal model greatly simplifies the system design, therefore the traditional trial-and-error procedure is deserted. The contrast simulation results indicate that the simplified model can represent the low-frequency big-signal dynamic behavior of the six-switch three-phase PFC circuit.