微型机与应用
微型機與應用
미형궤여응용
MICROCOMPUTER & ITS APPLICATIONS
2010年
7期
52-54,57
,共4页
正交幅度调制%流水线CORDIC%FPGA
正交幅度調製%流水線CORDIC%FPGA
정교폭도조제%류수선CORDIC%FPGA
QAM%pipeline CORDIC%FPGA
提出了一种基于流水线CORDIC的算法实现QAM调制,可有效节省硬件资源,提高运算速度.用Verilog HDL对本设计进行了编程和功能仿真,仿真结果表明,本设计具有一定的实用性.
提齣瞭一種基于流水線CORDIC的算法實現QAM調製,可有效節省硬件資源,提高運算速度.用Verilog HDL對本設計進行瞭編程和功能倣真,倣真結果錶明,本設計具有一定的實用性.
제출료일충기우류수선CORDIC적산법실현QAM조제,가유효절성경건자원,제고운산속도.용Verilog HDL대본설계진행료편정화공능방진,방진결과표명,본설계구유일정적실용성.
This paper puts forward a pipelined architecture for implementation of QAM on FPGA based on CORDIC algorithm, which can save considerable hardware resources and improve the speed performance. And programs this design with Verilog HDL and carries out functional simulation. The results show that this design is valuable and feasible in practice.
