山东科技大学学报：自然科学版
山東科技大學學報：自然科學版
산동과기대학학보：자연과학판
Journal of Shandong Univ of Sci and Technol: Nat Sci
2011年
6期
73-79,84
,共8页
超宽带%前端电路%低噪声放大器%混频器
超寬帶%前耑電路%低譟聲放大器%混頻器
초관대%전단전로%저조성방대기%혼빈기
ultra-wide band,front-end circuit%low-noise amplifier%mixer
使用TSMC0．18μmCMOS工艺实现3．1～8．0GHz超宽带接收机前端电路芯片设计，并利用ADS软件进行仿真、电路参数调整。电路架构包括：单端输入差动输出之超宽带低噪声放大器、Balun（Balance-unbalance）以及差动输入／输出的超宽带降频混频器，主要特点是在低噪声放大器输出端和混频器之间加入Balun，提升电路性能并减少芯片面积。芯片测试结果：在供给电压1.8V下，频宽为3．1～8.0GHz，S11〈-15。3dB，转换增益为24．6dB，功率消耗为37.98mW；包台接脚,芯片面积0．985（0.897×1.098）mm2。
使用TSMC0．18μmCMOS工藝實現3．1～8．0GHz超寬帶接收機前耑電路芯片設計，併利用ADS軟件進行倣真、電路參數調整。電路架構包括：單耑輸入差動輸齣之超寬帶低譟聲放大器、Balun（Balance-unbalance）以及差動輸入／輸齣的超寬帶降頻混頻器，主要特點是在低譟聲放大器輸齣耑和混頻器之間加入Balun，提升電路性能併減少芯片麵積。芯片測試結果：在供給電壓1.8V下，頻寬為3．1～8.0GHz，S11〈-15。3dB，轉換增益為24．6dB，功率消耗為37.98mW；包檯接腳,芯片麵積0．985（0.897×1.098）mm2。
사용TSMC0．18μmCMOS공예실현3．1～8．0GHz초관대접수궤전단전로심편설계，병이용ADS연건진행방진、전로삼수조정。전로가구포괄：단단수입차동수출지초관대저조성방대기、Balun（Balance-unbalance）이급차동수입／수출적초관대강빈혼빈기，주요특점시재저조성방대기수출단화혼빈기지간가입Balun，제승전로성능병감소심편면적。심편측시결과：재공급전압1.8V하，빈관위3．1～8.0GHz，S11〈-15。3dB，전환증익위24．6dB，공솔소모위37.98mW；포태접각,심편면적0．985（0.897×1.098）mm2。
A receiver front-end chip for ultra-wide band systems operating in 3.1-8.0 GHz frequency range was designed and successfully fabricated by TSMC 0. 18 μm CMOS process. All the circuits were simulated and tuned by simulator ADS （advanced design system）. The proposed chip uses the passive Balun to achieve the conversion between LNA and mixer and, the LNA uses the transformer as input matching to achieve low chip area and high performance. The measured results show that at the supply voltage of 1.8 V, the proposed chip is tunable from 3.1 to 8.0 GHz and obtains S, less than -15.3 dB,conversion gain （CGmax） of 24.6 dB and power consumption of 37.98 mW. Including pads,the total chip area is 0. 985 （0. 897× 1. 098） mm2.
