CAJ | 학술논문

根据硬件开销和缺陷的检测能力评估了一种可重构的调试设计方案.对于要调试的目标电路,首先设计并完成了一套由4个32位处理器核组成的多处理机系统,然后评估该调试设计电路的硬件架构.对改变调试电路排列的评估结果表明,调试电路的硬件开销占用所实现的多处理机系统在8.6%～12.7%的范围内.其次,对是否可以通过调试电路发现故障效应进行了评估.在一个16位处理器核上注入了10种不同的故障并且检查其是否会被每一个设置在处理器核上的观测点所发现,同时测量了观察所需的时钟周期数.最后还评估了每一种故障的可观察率以及每一个观察点的可观察率.
근거경건개소화결함적검측능력평고료일충가중구적조시설계방안.대우요조시적목표전로,수선설계병완성료일투유4개32위처리기핵조성적다처리궤계통,연후평고해조시설계전로적경건가구.대개변조시전로배렬적평고결과표명,조시전로적경건개소점용소실현적다처리궤계통재8.6%～12.7%적범위내.기차,대시부가이통과조시전로발현고장효응진행료평고.재일개16위처리기핵상주입료10충불동적고장병차검사기시부회피매일개설치재처리기핵상적관측점소발현,동시측량료관찰소수적시종주기수.최후환평고료매일충고장적가관찰솔이급매일개관찰점적가관찰솔.
In this study we evaluate the effectiveness of a reconfigurable design-for-debug scheme,in terms of hardware overhead and detection capability of bugs.For target circuit under debug,we first design and implement a multi-processor system consisting of four 32-bit processor cores,and then evaluate the hardware overhead of design-for-debug circuit.The evaluation result changing the arrangement of debug circuit indicates that the hardware overhead of debug circuit against the implemented multi-processor system was in the range of 8.6% to 12.7%.Next,we evaluate whether a fault effect can be observed or not by using debug circuit.On a 16-bit processor core we inject 10 different faults and checked whether a fault is observed at each observation point in the processor core,measuring the number of clock cycles required for observation.We also evaluated the rate of observability of each fault,as well as observability of each observation point.