CAJ | 학술논문

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2 nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流.为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视.然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性.在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5 nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3 nm的二氧化硅pMOSFET经过125℃和10.7MV/cm的电场1 h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差.在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16 V,可以符合90 nm工艺1 V特操作电压的安全范围内.
MOSFET기건계속미축칙갑겁양화층후도장지속감소,재0.13μm적기술갑겁이양화규적후도필수소우2 nm,연이여차박적양화층직접천투전류조성료명현적루전류.위료강저루전류,이양화규도입고농도적담여탈우등리자체담화제비담양화규수도고도중시.연이,탈우등리자체담화제비담양화규적일항고필시pMOSFET부편압온도적실은성.재차연구리측량료탈우등리자체담화제비담양화규pMOSFET부편압온도실은성,병차화전통적이양화규갑전겁비교,후도1.5 nm적탈우등리자체담화제비담양화규pMOSFET화후도1.3 nm적이양화규pMOSFET경과125℃화10.7MV/cm적전장1 h적응력하비교역치전압,결과현시탈우등리자체담화제비담양화규pMOSFET재부편압온도응력하성능교차.재15%역치전압개변적표준하,연장10년적수명,기최대공작전압시1.16 V,가이부합90 nm공예1 V특조작전압적안전범위내.
Continuous scaling-down of MOSFET devices has led to a constant reduction of the thickness of the gate oxide. For sub-0.13 μm gate length technologies, an equivalent SiO2 thickness lower than 2 nm is required. Nevertheless, such a low thickness result in gate leakage current increasing significantly because of directly tunneling. To reduce gate leakage current in highly scaled CMOSFETs, silicon oxide incorporated with high nitrogen concentration such as Decoupled Plasma Nitridation (DPN) Oxynitride have attracted much attention recently. However, one of the main concerns of DPN Oxynitride gate dielectric pMOSFETs is the poor Bias-Temperature Instability. In this study we have measured the negative bias-temperature Instability of DPN oxynitride MOSFETs, and compared with the benchmark conventional gate dielectric SiO2 devices. A thickness of 1.5 nm DPN oxyynitride and 1.3 nm SiO2 nMOSFETs has been compared by threshold voltage (Vt) shift at 125 ℃ and 10.7 MV/cm stress for Ih. The result shows that DPN process has worsen the CMOSFETs device performance under Bias Temperature Stress. The extrapolated maximum voltage for 10 years lifetime is 1.16 V for DPN pMOSFETs at failure criteria of 15% DVt. It shows that DPN MOSFETs can meet the required 1 V operation with 10% safety margin. The DPN gate has merits of simple process and full compatible to current VLSI process line.