CAJ | 학술논문

设计了一种新的用于电压控制振荡器的延迟单元,并与源级耦合差分延时单元的时钟抖动进行了比较.提出了基于低时钟抖动的锁相环环路参数的优化技术.在0.35μm CMOS工艺下进行1.25GHz Serdes流片,测试表明数据率为1.25GHz的高速串联输出的随机抖动均方根为2.3ps(归一化为0.0015UI),随机抖动标准偏差为0.0035UI.在1111100000的数据输出时相位噪声为-120dBc/Hz@100kHz.
설계료일충신적용우전압공제진탕기적연지단원,병여원급우합차분연시단원적시종두동진행료비교.제출료기우저시종두동적쇄상배배로삼수적우화기술.재0.35μm CMOS공예하진행1.25GHz Serdes류편,측시표명수거솔위1.25GHz적고속천련수출적수궤두동균방근위2.3ps(귀일화위0.0015UI),수궤두동표준편차위0.0035UI.재1111100000적수거수출시상위조성위-120dBc/Hz@100kHz.
A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison be- tween the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ (random jitter) RMS of 1.25GHz data rate series output is 2. 3ps (0. 0015UI) and RJ (1 sigma) is 0. 0035UI. A phase noise measurement shows-120dBc/Hz@100kHz at 1111100000 clock-pattern data out.