CAJ | 학술논문

网络处理器设计中的存储瓶颈问题是指网络处理进行FIB(forwarding information base)查表、QoS调度、计数器管理等操作对外部控制存储器访问的延时与网络处理性能难以匹配的问题.目前网络处理器设计采用并行处理的方法隐藏访存延时,但由于设计复杂性和功耗问题,大规模并行技术难以在40Gbps以上的网络处理中继续应用.对当前网络处理器中存储瓶颈问题及其解决方法进行研究,指出其局限性,并针对未来更高性能网络处理,如100Gbps接口网络处理的设计提出了一种新的网络处理模型.
망락처리기설계중적존저병경문제시지망락처리진행FIB(forwarding information base)사표、QoS조도、계수기관리등조작대외부공제존저기방문적연시여망락처이성능난이필배적문제.목전망락처리기설계채용병행처리적방법은장방존연시,단유우설계복잡성화공모문제,대규모병행기술난이재40Gbps이상적망락처리중계속응용.대당전망락처리기중존저병경문제급기해결방법진행연구,지출기국한성,병침대미래경고성능망락처리,여100Gbps접구망락처리적설계제출료일충신적망락처리모형.
Processing of FIB lookup,QoS scheduling,counter management result in memory bottleneck for network processors design.These processing need to access off-chip control memory,yet the access delay is difficult to match the high performance of network processors.Presently,network processors design adopts parallelism technique to hide memory access delay.But due to the problem of design complexity and power,the large-scale parallelism technique is difficult to be used over 40Gbps network processing.In this paper,memory bottleneck problem and its solving methods are studied,and their limitation is pointed out.Finally,a network processing module is proposed,which focuses on future high performance network are studied processors such as 1 00Gbps interface processing design.