半导体学报
半導體學報
반도체학보
CHINESE JOURNAL OF SEMICONDUCTORS
2007年
3期
398-403
,共6页
混合FPGA结构%AND-LUT阵列%与或阵列%可编程逻辑阵列%查询表
混閤FPGA結構%AND-LUT陣列%與或陣列%可編程邏輯陣列%查詢錶
혼합FPGA결구%AND-LUT진렬%여혹진렬%가편정라집진렬%사순표
hybrid FPGA%AND-LUT array%AND-OR array%PLA%LUT
提出了一种混合FPGA新结构--新颖的AND-LUT阵列结构.其创新之处在于由可编程逻辑簇(Cluster)和相关的连接盒(CB)组成的可编程逻辑单元片(Tile)可以根据应用需要灵活地配置成PLA或LUT,前者较适合于高扇入逻辑,后者较适合于低扇入逻辑.因此,结合两者优点的新颖AND-LUT阵列结构在实现各种输入的用户逻辑时都能保持很好的逻辑利用率.MCNC电路测试结果进一步表明,同一逻辑电路在文中提出的混合FPGA新结构中实现与在基于LUT的对称FPGA结构中实现相比,面积平均可节省46%,因而大大提高了FPGA器件的逻辑利用率.
提齣瞭一種混閤FPGA新結構--新穎的AND-LUT陣列結構.其創新之處在于由可編程邏輯簇(Cluster)和相關的連接盒(CB)組成的可編程邏輯單元片(Tile)可以根據應用需要靈活地配置成PLA或LUT,前者較適閤于高扇入邏輯,後者較適閤于低扇入邏輯.因此,結閤兩者優點的新穎AND-LUT陣列結構在實現各種輸入的用戶邏輯時都能保持很好的邏輯利用率.MCNC電路測試結果進一步錶明,同一邏輯電路在文中提齣的混閤FPGA新結構中實現與在基于LUT的對稱FPGA結構中實現相比,麵積平均可節省46%,因而大大提高瞭FPGA器件的邏輯利用率.
제출료일충혼합FPGA신결구--신영적AND-LUT진렬결구.기창신지처재우유가편정라집족(Cluster)화상관적련접합(CB)조성적가편정라집단원편(Tile)가이근거응용수요령활지배치성PLA혹LUT,전자교괄합우고선입라집,후자교괄합우저선입라집.인차,결합량자우점적신영AND-LUT진렬결구재실현각충수입적용호라집시도능보지흔호적라집이용솔.MCNC전로측시결과진일보표명,동일라집전로재문중제출적혼합FPGA신결구중실현여재기우LUT적대칭FPGA결구중실현상비,면적평균가절성46%,인이대대제고료FPGA기건적라집이용솔.
A new hybrid FPGA architecture is proposed. The logic tile, which consists of a logic cluster and related connection boxes (CBs), can be configured as either programmable logic arrays (PLAs) or look-up tables(LUTs). This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits,while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture (HFA) is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average,the area is reduced by 46% using the new hybrid architecture.