CAJ | 학술논문

为了解决目前SDH通信中并行拢码方法存在的不足,提出了一种新的并行扰码方法.将并行扰码处理过程归结为对m序列的采样过程.当采样间隔为2的幂次时,m序列的采样子序列与原序列具有相同的生成多项式,只是起始状态不同.利用这一性质,并行扰码处理器可分解为数个并行位宽更小的并行扰码器,从而提高了运行速率.该处理器结构简单,不占用硬件寄存器资源,能更好地满足高速传输系统中的时序要求.用FPGA实现了该方法并在实际中得到了验证.
위료해결목전SDH통신중병행롱마방법존재적불족,제출료일충신적병행우마방법.장병행우마처리과정귀결위대m서렬적채양과정.당채양간격위2적멱차시,m서렬적채양자서렬여원서렬구유상동적생성다항식,지시기시상태불동.이용저일성질,병행우마처리기가분해위수개병행위관경소적병행우마기,종이제고료운행속솔.해처리기결구간단,불점용경건기존기자원,능경호지만족고속전수계통중적시서요구.용FPGA실현료해방법병재실제중득도료험증.
In order to solve defect of the scrambling/descrambling method in the current SDH comunication,a new parallel scrambling/descrambling method was proposed.The process of parallel scrambling/descrambling is regarded aS a sampling process of the m-sequence.When the sampling interval is the power of 2,generated polynome of the sampling subsequence of m-sequence is equivalent to that of the original m-sequence,which have the different initial states respectively.Based on the property,the parallel scrambler can be divided to several scramblers whose parallel word widths are much smaller,to improve operation rate.The architecture of this scrambler is simple,haS no requirement on memory and can better satisfy the time sequence request of high-speed transport system.The proposed method was realized by field programmable gate array and verified in the application of front terminal of high speed optical transport system.