CAJ | 학술논문

提出一种新的纠正CORDIC算法中模因子的方法以解决传统方法所带来的电路结构不规则、系统吞吐率降低等弊端.首先根据迭代方程之间的关系,通过推导引入一个新的迭代方程,将模因子的校正过程转化为只需要移位和加法运算即可实现的简单的迭代过程.然后分析了该算法量化误差中的舍入误差所带来的影响,并提出该误差可以通过对迭代方程中的系数进行合适取值来降低.最后对提出的算法通过Matlab建模并利用Verilog HDL语言进行RTL级编程,经过综合后在FPGA上进行了验证.仿真结果表明,与传统方法相比,在相同精度条件下使用所提方法只需要额外的一个时钟周期即可达到模校正的目的,且不需要修改基本的迭代操作.因此电路实现比较规则,同时系统吞吐率变化较小.
제출일충신적규정CORDIC산법중모인자적방법이해결전통방법소대래적전로결구불규칙、계통탄토솔강저등폐단.수선근거질대방정지간적관계,통과추도인입일개신적질대방정,장모인자적교정과정전화위지수요이위화가법운산즉가실현적간단적질대과정.연후분석료해산법양화오차중적사입오차소대래적영향,병제출해오차가이통과대질대방정중적계수진행합괄취치래강저.최후대제출적산법통과Matlab건모병이용Verilog HDL어언진행RTL급편정,경과종합후재FPGA상진행료험증.방진결과표명,여전통방법상비,재상동정도조건하사용소제방법지수요액외적일개시종주기즉가체도모교정적목적,차불수요수개기본적질대조작.인차전로실현비교규칙,동시계통탄토솔변화교소.
To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer(CORDIC) algorithm is proposed.Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations.As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula.The model is then set up in Matlab and coded in Verilog HDL language.The proposed algorithm is also synthesized and verified in field-programmable gate array(FPGA).The resultsshow that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm.In addition, the circuit realization is regular and the change in system throughput is very minimal.