计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2009年
24期
257-258,261
,共3页
时钟%动态时钟管理%门控时钟%低功耗时钟树综合
時鐘%動態時鐘管理%門控時鐘%低功耗時鐘樹綜閤
시종%동태시종관리%문공시종%저공모시종수종합
clock%dynamic clock management%gated clock%low power consumption Clock Tree Synthesis(CTS)
针对时钟网络在SoC芯片中的作用和时钟网络自身的特点,研究并实现3种时钟低功耗技术,包括在系统级采用动态时钟管理技术动态地关断和配置芯片内各模块的时钟,在逻辑综合时基于功耗优化工具Power Compiler插入门控时钟单元,在时钟树综合时以时钟树规模为目标进行低功耗时钟树综合.在音视频解码芯片的设计中采用以上3种技术,结果表明其功耗优化效果明显.
針對時鐘網絡在SoC芯片中的作用和時鐘網絡自身的特點,研究併實現3種時鐘低功耗技術,包括在繫統級採用動態時鐘管理技術動態地關斷和配置芯片內各模塊的時鐘,在邏輯綜閤時基于功耗優化工具Power Compiler插入門控時鐘單元,在時鐘樹綜閤時以時鐘樹規模為目標進行低功耗時鐘樹綜閤.在音視頻解碼芯片的設計中採用以上3種技術,結果錶明其功耗優化效果明顯.
침대시종망락재SoC심편중적작용화시종망락자신적특점,연구병실현3충시종저공모기술,포괄재계통급채용동태시종관리기술동태지관단화배치심편내각모괴적시종,재라집종합시기우공모우화공구Power Compiler삽입문공시종단원,재시종수종합시이시종수규모위목표진행저공모시종수종합.재음시빈해마심편적설계중채용이상3충기술,결과표명기공모우화효과명현.
Aiming at clock network's function in SoC chip and its own characteristic, this paper studies and implements three kinds of clock low power consumption techniques including using dynamic clock management technique to cut down and distribute module's clock dynamicly in system level, inserting clock gating cells based on power consumption optimization tool named Power Compiler during logic synthesis, and doing a low power consumption Clock Tree Synthesis(CTS) targeting on clock tree's dimension during clock tree synthesis. These three techniques are implemented during the design of audio and video decoding chip, and the results show that their power consumption optimization effects are obvious.
