混合型判决反馈均衡器设计与FPGA实现
혼합형판결반궤균형기설계여FPGA실현
Design and FPGA implementation of decision feedback equalizer of hybrid architecture
  • 万方数据
    微型机与应用 미형궤여응용
    MICROCOMPUTER & ITS APPLICATIONS
    2012年 5期 54-56 ,共3页

    杨滔%宋学瑞%曹宏徙

    양도%송학서%조굉사

    判决反馈均衡%1000BASE—T%混合结构%网格译码 判決反饋均衡%1000BASE—T%混閤結構%網格譯碼
    판결반궤균형%1000BASE—T%혼합결구%망격역마
    decision feedback equalizer%1000BASE-T%hybrid architecture%trellis decoding
    针对1000BASE—T中的均衡解码结构，从信噪比与误码率、速度及硬件复杂度等方面比较了该判决反馈均衡解码器的几种形式，并设计了一种满足速度与误码率要求而硬件复杂度更低的混合型结构，该结构将部分残留后馈干扰级数移除，同时应用流水线及重定时技术优化其性能。
    침대1000BASE—T중적균형해마결구，종신조비여오마솔、속도급경건복잡도등방면비교료해판결반궤균형해마기적궤충형식，병설계료일충만족속도여오마솔요구이경건복잡도경저적혼합형결구，해결구장부분잔류후궤간우급수이제，동시응용류수선급중정시기술우화기성능。
    This paper compares several architectures according to SNR and bit error ratio, speed and hardware cost. A hybrid architecture is proposed which meets the speed and bit error requirements and has lower hardware cost. It removes the less significant ISI by a pre-equalizer, and applies pipelining and retiming technologies to improve its performance.
    원문보기 원문다운로드 사이트로이동
저자의 최근 논문