CAJ | 학술논문

在数字集成电路设计中,时序收敛是保证芯片性能的关键,但随着集成电路制造工艺的不断发展,芯片规模不断增加,结构日趋复杂,时序收敛的难度也逐渐加大。该文针对数字音频广播基带解码芯片的后端设计,分析了造成时序违例的原因,并在综合、布图规划、布局等阶段提出了对应的时序收敛策略,最终使芯片满足了系统的时序要求。
재수자집성전로설계중,시서수렴시보증심편성능적관건,단수착집성전로제조공예적불단발전,심편규모불단증가,결구일추복잡,시서수렴적난도야축점가대。해문침대수자음빈엄파기대해마심편적후단설계,분석료조성시서위례적원인,병재종합、포도규화、포국등계단제출료대응적시서수렴책략,최종사심편만족료계통적시서요구。
In digital circuit design,the key to ensure the function of a chip is timing closure,with the development of the process technology,the scale of the chip continue growing,and the configuration becomes more complexity,therefore implementation of timing closure is more and more difficult.For ASIC design of Digital Audio Broadcasting baseband IC,analyses the reason of timing violation first,then propose the relative strategies in synthesis,floorplan,placement etc,the proposed strategies enabled baseband IC to meet timing requirement of the system at last.