CAJ | 학술논문

提出了一种带时间延迟积分功能的高性能CMOS读出电路芯片适用的高效率电荷延迟线结构. 基于该结构,设计了一款288×4规格焦平面阵列组件适用的CMOS读出电路芯片,并已完成流片、测试.该芯片包括4个视频输出端,每个端口的像元输出频率为4～5MHz(如用于实现384×288规模的成像,帧频可达160Hz).测试结果表明这款芯片具有高动态范围(大于78dB)、高线性度(大于99.5%)、高均匀性(大于96.8%)等特征.
제출료일충대시간연지적분공능적고성능CMOS독출전로심편괄용적고효솔전하연지선결구. 기우해결구,설계료일관288×4규격초평면진렬조건괄용적CMOS독출전로심편,병이완성류편、측시.해심편포괄4개시빈수출단,매개단구적상원수출빈솔위4～5MHz(여용우실현384×288규모적성상,정빈가체160Hz).측시결과표명저관심편구유고동태범위(대우78dB)、고선성도(대우99.5%)、고균균성(대우96.8%)등특정.
A high efficient analog charge delay line (ACDL) is proposed. These analog delay lines can be used to realize high performance CMOS readout integrated circuits (ROIC) with time delay integration (TDI) function. A CMOS ROIC for 288×4 IRFPA were designed, manufactured, and tested. The chip has 4 video outputs, whose pix el frequency is 4-5MHz (for 384×288 format, its frame fr equency can achieve 160Hz). Test results show that this chip has high dyna mic range (>78dB), high linearity (>99.5%), and high uniformity (96.8% ).