CAJ | 학술논문

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.
성공지시제출박허의SiGe츤저상적응변Si pMOSFETs.이용분자속외연기술재100nm저온Si(LT-Si)완충층상생장적이예허의Si0.8Ge0.2츤저가감박지240nm.저온Si완충층용우석방허의SiGe츤저적응력,사기응변이예.X사선쌍정연사화원자력현미경측시표명:허의SiGe츤저적응변이예도위85%,표면평균조조도부위1.02nm.재실온하,응변Si pMOSFETs적최대천이솔체도140cm2/(V·s).기건성능략우우채용궤미미후허의SiGe츤저적기건.
Strained-Si pMOSFETs on very thin relaxed virtual SiGe substrates are presented. The 240nm relaxed virtual Si0. 8Ge0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy. LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed. DCXRD, AFM, and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85 % ,RMS roughness is 1.02nm,and threading dislocation density is at most 107 cm-2. At room temperature,a maximum hole mobility of strained-Si pMOSFET is al SiGe substrates.