一种实现高速异步FIFO的FPGA方法
일충실현고속이보FIFO적FPGA방법
Implementation method of high-speed asynchronous FIFO using FPGA
  • 万方数据
    计算机工程与应用 계산궤공정여응용
    COMPUTER ENGINEERING AND APPLICATIONS
    2010年 3期 13-15,26 ,共4页

    黄忠朝%赵于前

    황충조%조우전

    现场可编程门阵列(FPGA)%亚稳态%格雷码%高速FIFO 現場可編程門陣列(FPGA)%亞穩態%格雷碼%高速FIFO
    현장가편정문진렬(FPGA)%아은태%격뢰마%고속FIFO
    Field-Programmable Gate Array(FPGA)%metastability%gray-code%high-speed FIFO
    在跨时钟域传递数据的系统中,常采用异步FIFO(First In First Out,先进先出队列)口来缓冲传输的数据,以克服亚稳态产生的错误,保证数据的正确传输.但由于常规异步FIFO模块中的RAM存储器读写寻址指针常采用格雷码计数器以及"空满"控制逻辑的存在,将使通过这两个模块的信号通路延时对整个模块的工作频率造成制约.提出了一种在FPGA内实现高速异步FI-FO的方法,该方法针对不可能产生满信号的高频系统,通过省略"满"信号产生模块和多余的存储器位深来简化常规的FIFO模块,而只保留"空"信号产生模块.仿真和综合设计结果表明,整个模块的工作频率得到一定提高.
    재과시종역전체수거적계통중,상채용이보FIFO(First In First Out,선진선출대렬)구래완충전수적수거,이극복아은태산생적착오,보증수거적정학전수.단유우상규이보FIFO모괴중적RAM존저기독사심지지침상채용격뢰마계수기이급"공만"공제라집적존재,장사통과저량개모괴적신호통로연시대정개모괴적공작빈솔조성제약.제출료일충재FPGA내실현고속이보FI-FO적방법,해방법침대불가능산생만신호적고빈계통,통과성략"만"신호산생모괴화다여적존저기위심래간화상규적FIFO모괴,이지보류"공"신호산생모괴.방진화종합설계결과표명,정개모괴적공작빈솔득도일정제고.
    To overcome the metastability and ensure the validation of data transfer,the asynchronous First In First Out(FIFO) modules are often used to buffer data in systems with data transfers crossing clock domains.Because of the existence of the ad-dressing pointers,which often adopt Gray-code counters,and the "full & empty" generation logic in a usual asynchronous FIFO module,the signals passing two modules may suffer large delay.As a result,the working frequency of the whole module is limited. Based on a premise that the"full" state will never occur in a high-frequency system,a method of implementing high speed asyn-chronous FIFO in FPGA is proposed.The focus on this way is that the "full" flag generation logic and redundant RAM depth are omitted,i.e.,ouly the "empty" flag is generated.So,the design of FIFO is simplified.The results from simulation and synthesis de-sign show that the working speed of the whole module is greatly increased.
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