CAJ | 학술논문

为了使FPGA(field grogrammable gate array)布局系统能够处理含有快速进位链及IP(intellectual property)核的复杂电路,在模拟退火算法的基础上,提出一种新的FPGA布局算法.该算法对含有快速进位链和不含快速进位链的电模块分别构造和调用不同的评价函数.以此来优化布局系统,实验结果表明,此布局系统与最具代表性的VPR(versatile place and route)布局系统相比增加了处理进位链和IP核功能,提高了布局系统性能.
위료사FPGA(field grogrammable gate array)포국계통능구처리함유쾌속진위련급IP(intellectual property)핵적복잡전로,재모의퇴화산법적기출상,제출일충신적FPGA포국산법.해산법대함유쾌속진위련화불함쾌속진위련적전모괴분별구조화조용불동적평개함수.이차래우화포국계통,실험결과표명,차포국계통여최구대표성적VPR(versatile place and route)포국계통상비증가료처리진위련화IP핵공능,제고료포국계통성능.
In order to make the FPGA placement system can process the complex circuits with fast carry chain and IP(intellectual property)cores, this paper brought forward a new FPGA placement algorithm based on simulated annealing algorithm .The algorithm could construct and use different cost functions for the circuit modules with and without fast carry chain. And in this way, the placement system could be optimized. The experimentation results show that, compared with the most representative placement system, VPR(versatile place and route), the system proposed in this paper has the function of processing fast carry chain and IP cores, and improves the performance of the placement system.