CAJ | 학술논문

为了满足工业上数据采集的自适应需要,本文采用FPGA设计实现了高速数据采集,整个系统分为高速数据采集模块、数据缓冲模块、数据存储模块。其中数据采集模块对滤波放大后的输入信号进行采样,采样率可调;数据缓冲模块负责对采样得到的数据进行缓存：数据存储模块负责将缓存后的数据传输至存储器进行存储。使用Quartus Ⅱ仿真工具对各子模块功能进行了时序仿真,最后介绍了本设计中制作的两块电路板并加以调试,测试结果表明本设计满足系统指标。
위료만족공업상수거채집적자괄응수요,본문채용FPGA설계실현료고속수거채집,정개계통분위고속수거채집모괴、수거완충모괴、수거존저모괴。기중수거채집모괴대려파방대후적수입신호진행채양,채양솔가조;수거완충모괴부책대채양득도적수거진행완존：수거존저모괴부책장완존후적수거전수지존저기진행존저。사용Quartus Ⅱ방진공구대각자모괴공능진행료시서방진,최후개소료본설계중제작적량괴전로판병가이조시,측시결과표명본설계만족계통지표。
In order to meet an adaptive data acquisition industry needs,This design realizes high speed acquisition with the FPGA.The wholes system consists of high speed data acquisition module,data buffer module and data storage module.Data acquisition module regulates the sample rate to sample the analogdata after the signal is filtered and magnified.Data buffer module takes charge of caching the sample data and then the last module will transport them to the memory for storage.This paper uses the Quartus Ⅱ simulation tools to simulate the timing three submodules and finally describes the two circuit boards used in this design.The test results prove that this design satisfies the system requirements.