CAJ | 학술논문

提出了一种改进总线翻转编码方法,用于抑制高速集成电路系统中的同步开关噪声.该方法可以显著减少总线平均翻转比特位数,同时尽可能使总线相邻位保持奇模传输,有利于改善信号完整性.利用FPGA实现了提出的改进总线翻转编码模块.物理实验表明,相对总线翻转编码,该方法以功耗稍有增加的代价,可取得平均翻转数量减少15.17%、电源波动噪声减小22.34%的编码增益.
제출료일충개진총선번전편마방법,용우억제고속집성전로계통중적동보개관조성.해방법가이현저감소총선평균번전비특위수,동시진가능사총선상린위보지기모전수,유리우개선신호완정성.이용FPGA실현료제출적개진총선번전편마모괴.물리실험표명,상대총선번전편마,해방법이공모초유증가적대개,가취득평균번전수량감소15.17%、전원파동조성감소22.34%적편마증익.
A bus-invert encoding method was improved for simultaneous switching noise reduction in high speed IC system.The method greatly reduces the average inverting bits of data-bus and keeps adjacent bus line transmission in odd mode for signal integrity.The proposed bus-invert encoding module was implemented in FPGA.Test results showed that, with a slight power increase, average transition time decreased by 15.17% and voltage fluctuation noise was reduced by 22.34%.