CAJ | 학술논문

首次提出一种自适应节能方法用于设计4/5高速双模预分频器,它的特点是工作在除4模式时,其中一个D类触发器处于休眠状态.使用台积电混合信号0.25μm CMOS工艺,采用这一自适应节能的设计方法,设计了一个具有源极耦合结构的4/5高速舣模预分频器.仿真结果证明,这一新型4/5高速双模预分频器不受休眠到工作转换状态的影响,最高工作频率保持不变.同时,流片结果表明,当这一新型高速预分频器用于实现66/67分频时,可节省高达20%以上的功耗.
수차제출일충자괄응절능방법용우설계4/5고속쌍모예분빈기,타적특점시공작재제4모식시,기중일개D류촉발기처우휴면상태.사용태적전혼합신호0.25μm CMOS공예,채용저일자괄응절능적설계방법,설계료일개구유원겁우합결구적4/5고속의모예분빈기.방진결과증명,저일신형4/5고속쌍모예분빈기불수휴면도공작전환상태적영향,최고공작빈솔보지불변.동시,류편결과표명,당저일신형고속예분빈기용우실현66/67분빈시,가절성고체20%이상적공모.
An"automatic power down"method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode.Implemented with the TSMC 0.25μm mixed-sig-nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique.The simulation results show that the new 4/5 prescaler is immune to the"wake-up"issue and thereby retains the same maxi-mum operating frequency as the conventional prescaler.An integer-N divider with this proposed prescaler and with the di-vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the convention-al 4/5 prescaler.