0.18μm CMOS 20Gb/s 1:2分接器设计
0.18μm CMOS 20Gb/s 1:2분접기설계
20Gb/s 1: 2 Demultiplexer in 0. 18μm CMOS
  • 万方数据
    半导体学报 반도체학보
    CHINESE JOURNAL OF SEMICONDUCTORS
    2005年 10期 1881-1885 ,共5页

    王贵%王志功%王欢%丁敬峰%熊明珍

    왕귀%왕지공%왕환%정경봉%웅명진

    分接器%锁存器%CMOS%高速电路 分接器%鎖存器%CMOS%高速電路
    분접기%쇄존기%CMOS%고속전로
    demultiplexer%latch%CMOS%high-speed circuit
    使用标准0.18μm CMOS工艺设计并实现了1:2分接器.核心电路单元采用一种新的高速、低电压锁存器结构实现.与传统的源极耦合场效应管逻辑结构的锁存器相比,其电源电压更低且速度更快.此外,为了拓展带宽,在缓冲放大电路中采用了负反馈.测试结果表明芯片可以工作于20Gb/s数据速率下.电源电压为1.8V时,包括缓冲电路在内整个芯片的工作电流为72mA.
    사용표준0.18μm CMOS공예설계병실현료1:2분접기.핵심전로단원채용일충신적고속、저전압쇄존기결구실현.여전통적원겁우합장효응관라집결구적쇄존기상비,기전원전압경저차속도경쾌.차외,위료탁전대관,재완충방대전로중채용료부반궤.측시결과표명심편가이공작우20Gb/s수거속솔하.전원전압위1.8V시,포괄완충전로재내정개심편적공작전류위72mA.
    A 1:2 demultiplexer is designed and realized in standard 0.18μm CMOS technology.A novel high-speed and low-voltage latch is used to realize the core circuit cell.Compared to the traditional source-coupled FET logic structure latch,its power supply voltage is lower and the speed is faster.In addition,the negative feedback is used in the buffer circuit to widen its bandwidth.Measurement results show that the chip can work at the data rate of 20Gb/s.The supply voltage is 1.8V and the current,including the buffer circuit,is 72mA.
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