CAJ | 학술논문

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.
재이용분자속외연방법제비SiGe pMOSFET중인입료저온Si기술.통과재Si완충층화SiGe층지간가입저온Si층,제고료SiGe층적이예도.당Ge주분위20%시,이용저온Si기술생장적이예Si1-xGex층적후도유UHVCVD제비소수적수미미강지400nm이내,AFM측시표명기표면균방조조도(RMS)소우1.02nm.기건측시표명,여상동제비과정적체규pMOSFET상비,공혈천이솔최대제고료25%.
A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At the same time,the threading dislocations (TDs) are hold back from propagating to the surface.As a result,the thickness of relaxed Si1-xGex epitaxy layer on bulk silicon is reduced from several micrometers using UHVCVD to less than 400nm(x=0.2),which will improve the heat dissipation of devices.AFM tests of strained Si surface show RMS is less than 1.02nm.The DC characters measured by HP 4155B indicate that hole mobility μp has 25% of maximum enhancement compared to that of bulk Si pMOSFET processed similarly.