CAJ | 학술논문

针对输入信号频率在20 Hz~24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗∑△模数调制器.在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW.该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗.另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本.与近期报道的低压低功耗∑△模数调制器相比,该设计具有更高的品质因子FOM.
침대수입신호빈솔재20 Hz~24 kHz범위적음빈응용,해문채용표준수자공예설계료일개1.2 V전원전압16위정도적저압저공모∑△모수조제기.재6 MHz채양빈솔하,해조제기신조비위102.2 dB,정개전로공모위2.46 mW.해조제기채용일충위량급교호공제적쌍수입운산방대기구성각급적분기,재저전원전압정황하실현고파솔고증익요구적동시불회산생경다공모.령외,채용고선성도、전호보MOS모진전용작위채양、적분전용사득정개전로가이채용표준수자공예실현,종이제고전로적공예겸용성、강저전로성본.여근기보도적저압저공모∑△모수조제기상비,해설계구유경고적품질인자FOM.
For audio signals with input frequency between 20 Hz and 24 kHz, a switch-capacitor feed-forward ∑△A/D modulator in 0.18μm Logic technology is proposed in this paper, which gains 16 bit resolution with 1.2 V supply voltage. The modulator can achieve 102.2 dB signal-to-noise ratio (SNR) under 6MHz sample clock, and the total power dissipation is only 2.46 mW. In the modulator, a pseudo-two-stage Class-AB transconductance amplifier is used, which has high slew rate and open loop gain while without increasing power dissipation. What is more, full compensated depletion-mode capacitors are used as sample capacitors and integrating capacitors to enable the whole chip to be fabricated in standard digital technology, which is good to reduce chip cost and improve the modulators' compatibility in technology. Compared with other low-power low-voltage ∑△A/D modulators reported, this design has better FOM (Figure Of Merit).