计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2010年
5期
250-252
,共3页
可重构计算%部分可重构%动态可重构%现场可编程门阵列
可重構計算%部分可重構%動態可重構%現場可編程門陣列
가중구계산%부분가중구%동태가중구%현장가편정문진렬
reconfigurable computing%partial reconfigurable%dynamic reconfigurable%Field Programmable Gate Array(FPGA)
针对现有可重构计算硬件平台配置时间长、灵活性受限的缺陷,提出一种改进设计.基于支持二维重构区域的Virtex-4现场可编程门阵列(FPGA)芯片,使重构模块放置更灵活、芯片面积利用率更高,通过将单片FPGA和外设集成在一块印刷电路板上,使系统的结构更紧凑,利用FPGA内嵌微处理器减轻通信和访存开销.调试结果表明,改进平台灵活性较高、功能和可扩展性更强.
針對現有可重構計算硬件平檯配置時間長、靈活性受限的缺陷,提齣一種改進設計.基于支持二維重構區域的Virtex-4現場可編程門陣列(FPGA)芯片,使重構模塊放置更靈活、芯片麵積利用率更高,通過將單片FPGA和外設集成在一塊印刷電路闆上,使繫統的結構更緊湊,利用FPGA內嵌微處理器減輕通信和訪存開銷.調試結果錶明,改進平檯靈活性較高、功能和可擴展性更彊.
침대현유가중구계산경건평태배치시간장、령활성수한적결함,제출일충개진설계.기우지지이유중구구역적Virtex-4현장가편정문진렬(FPGA)심편,사중구모괴방치경령활、심편면적이용솔경고,통과장단편FPGA화외설집성재일괴인쇄전로판상,사계통적결구경긴주,이용FPGA내감미처리기감경통신화방존개소.조시결과표명,개진평태령활성교고、공능화가확전성경강.
Aiming at the shortage of long configuration time and flexibility constrained for existing reconfigurable computing hardware platform,this paper proposes an improved design.Based on Virtex-4 Field Programmable Gate Array(FPGA)chip supporting 2D reconstructed area,it makes the module placement faster and higher utilization of chip area,makes more compact of system structure through integrating single FPGA and extras in a printing circuit diagram,uses FPGA embedded microprocessor to reduce cost of communication and access memory.Debugging result shows that improved platform is more flexible,function and extendibility is more strong.
