CAJ | 학술논문

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.
재심아미미설계중,강저능모화전파연지시편상전국총선소면대적량개최주요설계목표.본문제출료일충용우편상전국총선적시공편마방안,타기제고료성능우강저료봉치능모화평균능모.해편마방안이용공간총선도상편마화시간편마전로기술적우점,재소제상린련선상반상번전적동시,감소료자번전수화우합번전수.재응용해총선편마기술강저총선연시화능모적설계중,급출료일충총선상삽입중계구동기적설계방법,이학정타문합괄적척촌화삽입위치,사득재만족목표연시화번전사솔요구적동시총선총적능모최소.해방법가용래위각충편마기술획득번전사솔약속하적총선능모여연시적우화절중.
On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length,which minimizes the total bus energy dissipation while satisfying target delay and slewrate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.