CAJ | 학술논문

为在设计阶段快速评估集成电路的软错误率,以指导高可靠集成电路的设计,提出一种适用于组合逻辑电路和时序逻辑电路组合逻辑部分的快速软错误率自动分析平台HSECT-ANLY.采用精确的屏蔽概率计算模型来分析软错误脉冲在电路中的传播;用向量传播和状态概率传播的方法来克服重汇聚路径的影响,以提高分析速度;使用LL(k)语法分析技术自动解析Verilog网表,使分析过程自动化,且使得本平台可分析时序电路的组合逻辑部分.开发工作针对综合后Verilog网表和通用的标准单元库完成,使得HSECT-ANLY的实用性更强.对ISCAS'85和ISCAS'89 Benchmark电路进行分析实验的结果表明:文中方法取得了与同类文献相似的结果,且速度更快,适用电路类型更多,可自动分析电路的软错误率并指导高可靠集成电路的设计.
위재설계계단쾌속평고집성전로적연착오솔,이지도고가고집성전로적설계,제출일충괄용우조합라집전로화시서라집전로조합라집부분적쾌속연착오솔자동분석평태HSECT-ANLY.채용정학적병폐개솔계산모형래분석연착오맥충재전로중적전파;용향량전파화상태개솔전파적방법래극복중회취로경적영향,이제고분석속도;사용LL(k)어법분석기술자동해석Verilog망표,사분석과정자동화,차사득본평태가분석시서전로적조합라집부분.개발공작침대종합후Verilog망표화통용적표준단원고완성,사득HSECT-ANLY적실용성경강.대ISCAS'85화ISCAS'89 Benchmark전로진행분석실험적결과표명:문중방법취득료여동류문헌상사적결과,차속도경쾌,괄용전로류형경다,가자동분석전로적연착오솔병지도고가고집성전로적설계.
A novel SER analysis platform,called HSECT-ANLY,was developed to rapidly calculate the soft error rate (SER) of integrated circuits for the design of high reliable integrated circuits.HSECT-ANLY is suitable for the automated SER analysis of both the pure combinational logic circuits and the combinational part of sequential logic circuit.It uses accurate masking probability model to characterize the propagating of soft error glitches and uses input vector propagating and state probability propagating technique to overcome the deficiency of reconvergent paths with considerable speed gains.LL(k) syntax analysis technique is employed to parse the Verilog netlist to automate the analysis process and make the combinational part of sequential logic circuit analyzable.The platform was developed based on synthesized Verilog netlist and common standard cell library,which made it more practical than the other tools.By using HSECT-ANLY,experiments were carried out on ISCAS'85 and ISCAS'89 benchmark circuits and comparable results to the previous works were got with faster speed and more applicable circuit types.Experimental results show that the technique is appropriate to analyze the SER of module circuits and to direct the design of high reliability integrated circuits.